Performance Engineer:

• Created and supported tools and infrastructure for large-scale sweep experiments in interconnect system analysis.
• Developed a library around IBM Spectrum LSF for flexible job offloading and better orchestration in HPC clusters.
• Supported performance model productization via python scripts to stitch GUI application outputs to model inputs.
• Dynamically mapped registers between the RTL and performance model for the hardware emulation team.

RTL Design Rotation:

• Added ASIL-B compliant RTL parity and interface checkers in AXI-Stream blocks.
• Extended support for new RTL features to existing python-based verilog generator tools.

Formal Verification Rotation:

• Designed formal testbench for compression and AMU blocks, working with their respective RTL owners.
• Improved a protocol domain bridge testbench in collaboration with the formal team.

• Performance analysis on Data Streaming Accelerator (DSA), an on-chip accelerator found on newer Intel Xeon processors.
• Explored use cases for DSA to take advantage of cache pollution mitigation and higher throughput for memory operations.
• Submitted patents for improving memory deduplication techniques using DSA
• Prepared and Presented a tutorial for Intel's on-chip accelerators at ISCA 2023 - earned Intel's internal Department Recognition Award.

• Investigated the effectiveness of an L1 cache in a CXL device for DLRM offloading.
• Built a cache simulator to evaluate both hit rates and cache occupancy rates of real-world DLRM memory traces.
• Analyzed the characteristics of the DLRM data for locality patterns to aid in the design of the memory system.
• Simulated DRAM and cache designs in Ramulator to obtain bandwidth, hit rate, and other metrics used in analysis.

• Debugged failing signatures for the CPU memory system testbench.
• Implemented new statistical coverage (SCOV) workflow:
• Used scoreboard listener functions to implement SCOV events for assessing stimulus coverage.
• Coded macro for ease of adding additional SCOV events within the UVM testbench.
• Developed Python script to parse generated simulation log files during regression tests to send to a MySQL database.

• Developed python script to analyze the use of all plusargs within the UVM testbenches.
• Scripted two githooks for file update notifications.
• Fixed UVM register definition autogeneration for more flexible RAL models.
• Programmed module for modeling transactions between a master device to interconnect return nodes in SystemC.
• Formally verified round robin and LSB priority arbiters using system verilog assertions.

• Improved kernel ION memory allocation speeds by ~10%.
• Analyzed the efficiency of IOVA’s use of caching and compared it with mmap’s gap searching RBTree structure.
• Created internal python file tracing tool for parsing Linux RAM dump binaries.
• Worked towards shifting mmap allocations to use the mempool API.