Hi, I'm Reese!

I'm an ECE graduate student at the University of Illinois at Urbana Champaign focusing on computer architecture.

Education

  • AP Physics C - E&M5
  • AP Physics C - Mechanics5
  • AP Physics 25
  • AP Physics 14
  • AP Calculus BC & AB Subscore5
  • AP Chemistry5
  • AP Statistics5
  • AP Psychology5
  • Parallel Computer Architecture
  • Computer Architecture
  • Digital Design and Synthesis
  • Parallel Programming
  • Operating Systems
  • Algorithms
  • Artificial Intelligence
  • OOP and Data Structures
  • Advanced Computer Architecture
  • Computer Microarchitecture
  • System-on-Chip Design
  • Memory and Storage Systems
  • Programming Languages and Compilers

Experience

  • Improved kernel ION memory allocation speeds by ~10%
  • Analyzed the efficiency of IOVA’s use of caching and compared it with MMAP’s gap searching RBTree structure
  • Created internal python file tracing tool for parsing Linux RAM dump binaries
  • Worked towards shifting mmap allocations to use the mempool API
  • Developed python script to analyze the use of all plusargs within the UVM testbenches
  • Scripted two githooks for file update notifications
  • Fixed UVM register definition autogeneration for more flexible RAL models
  • Programmed module for modeling transactions between a master device to interconnect return nodes in SystemC
  • Formally verified round robin and LSB priority arbiters using system verilog assertions
  • Debugged failing signatures for the CPU memory system testbench
  • Implemented new statistical coverage (SCOV) workflow:
    • Used scoreboard listener functions to implement SCOV events for assessing stimulus coverage
    • Coded macro for ease of adding additional SCOV events within the UVM testbench
    • Developed Python script to parse generated simulation log files during regression tests to send to a MySQL database
  • Investigated the effectiveness of an L1 cache in a CXL device for DLRM offloading
  • Built a functional cache simulator to evaluate both hit rates and cache occupancy rates of real DLRM memory traces
  • Analyzed the characteristics of real DLRM data for locality patterns to aid in the design of the memory system
  • Simulated DRAM and cache designs via Ramulator to obtain bandwidth, hit rate, and other metrics used in analysis
  • Conducted performance analysis on DSA - an on-chip accelerator found on Sapphire Rapids and later Xeon processors
  • Explored use cases for DSA to take advantage of cache pollution mitigation and higher throughput for memory operations
  • Submitted patents for improving memory deduplication techniques using DSA
  • Prepared and Presented a tutorial for Intel's on-chip accelerators at ISCA 2023 - earned Intel's internal Department Recognition Award
  • Built several large performance tooling scripts

Publications and Patents

A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors

Reese Kuper, Ipoom Jeong, Yifan Yuan, Ren Wang, Narayan Ranganathan, Nikhil Rao, Jiayu Hu, Sanjay Kumar, Philip Lantz, Nam Sung Kim

[PAPER] International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). April, 2024

[PAPER] Open-access ePrint Archive (arXiv). April, 2023

Efficiently Merging Non-Identical Pages in Kernel Same-Page Merging (KSM) for Efficient and Improved Memory Deduplication and Security

Reese Kuper, Yifan Yuan, Ren Wang

[PATENT] US Patent App 18/369,090. 2024

Method and Appratus for Batching Pages for a Data Movement Accelerator

Reese Kuper, Yifan Yuan, Ren Wang

[PATENT] US Patent App 18/477,628. 2024

Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices

Yan Sun, Yifan Yuan, Zeduo Yu, Chihun Song, Reese Kuper, Jinghan Huang, Houxiang Ji, Siddharth Agarwal, Jiaqi Lou, Ipoom Jeong, Ren Wang, Jung Ho Ahn, Tianyin Xu, Nam Sung Kim

[PAPER] International Symposium on Microarchitecture (MICRO). October, 2023

[PAPER] Open-access ePrint Archive (arXiv). April, 2023

On-chip Accelerators in 4th Gen Intel® Xeon® Scalable Processors: Features, Performance, Use Cases, and Future!

Reese Kuper, Ipoom Jeong, Yifan Yuan, Jiayu Hu, Ren Wang, Narayan Ranganathan, Nam Sung Kim

[TUTORIAL] International Symposium on Computer Architecture (ISCA). June, 2023

STYX: Exploiting SmartNIC Capability to Reduce Datacenter Memory Tax

Houxiang Ji, Yan Sun, Mark Mansi, Yifan Yuan, Jinghan Huang, Reese Kuper, Michael Swift, Nam Sung Kim

[PAPER] The USENIX Annual Technical Conference (ATC). July, 2023

Improving GPU Utilization in ML Workloads Through Finer-Grained Synchronization

Reese Kuper, Suchita Pati, Matthew D. Sinclair

[PAPER] Young Architect Workshop (YArch). April, 2021

Contact

Website made by Reese Kuper